1. Field of the Invention
The present invention is related to a system for checking data parity errors in real time during transmission of data from a transmitter to a bus and again in real time during transmission of data from a bus to a receiver. More particularly, the present invention is related to novel fault indicating circuits which are placed in series between elements of a high-speed storage unit and the read and write buses for detecting errors in data transmission to and from the elements of the storage unit. The fault indicating circuits are capable of indicating the element at fault, the slice or block of the element at fault and the type of fault even though the elements are hard wired or connected to the read/write buses.
2. Description of the Prior Art
Modern high-speed main frame computers employ parity checking circuits and parity checking systems when accessing information from high-speed cache memories. Such systems are described in U.S. Pat. No. 4,168,541 Filed also in U.S. application Ser. No. 07/241,421 7 Sept. 1988. entitled High-Speed Partition Set Associative Cache Memory. This latter Application shows and describes logic for identifying the block or array in which a data parity error has occurred when memory is accessed and the data is placed on an output bus or transmission line. Thus, the parity checking circuits can identify a parity error associated with the information being transmitted from a particular block or card which will enable maintenance personnel to be able to replace the complete storage array board and/or disable a portion of the memory if the memory remains in operation.
Main storage units for high-speed main frame computers that employ separate read and write buses also check the parity of the data being transmitted onto the read or write bus. When the elements of the main storage units are hardwired or connected to the read or write bus, it is possible to identify the element (card or board) which generated the faulty data but prior art parity check circuits do not identify faults which are generated by the circuitry associated with the board or card.
Modern high-speed computers employ storage elements on cards or boards which are densely populated with semiconductor devices. Such storage elements divide words into bytes which are associated with a single board. Prior art parity checking circuits are adapted to indicate the card or plugable storage element which generated the errors if the error checking circuits are not at fault, but do not provide means for indicating whether the error checking circuit themselves or the logic circuitry portion of the board or card generated the error signal.
High-speed main frame computers are being operated at clock cycles approaching thirty (30) nanoseconds (n sec). The clock cycles are subdivided into subdivisions or phases which are so small that very few logic decisions can occur during a clock phase of a high-speed clock. For example, switching times of high-speed logic elements are now approaching one nanosecond and clock phase times are well under ten nanoseconds which permits very few complex logic decisions during a clock phase cycle. Further, delays in the bus paths and line communication paths consume a very large portion of any clock phase time during a clock cycle.
There is currently a need for a high-speed parity checking circuit which can be operating during real transmission time of the data to and from a bus without delaying the transmission and reception of the data.